This invention relates to a tri-well CMOS structure and method of manufacture which provides at least three kinds of active regions for device formation. The active regions may include lightly doped regions of either N or P type for the formation of devices having a high breakdown voltage, moderately to heavily doped P wells for N channel devices having a low breakdown voltage, and moderately to heavily doped N well regions for P channel devices having a low breakdown voltage.
A prior art P well CMOS structure is illustrated in FIG. 1a. P well 1 is diffused into a silicon substrate 2. Silicon substrate 2 has been moderately doped with N type dopants to a level within the range of approximately 2.times.10.sup.15 to 4.times.10.sup.15 atoms/cm.sup.3. Source and drain regions 4 and 5 respectively of an N channel device 3 having a gate 6 are then formed in P well 1, and source and drain regions 8 and 9 of a P channel device 7 having a gate 10 are formed in N type substrate 2.
In practice, due to processing variations, there is some deviation between the actual doping levels achieved in the P well and the N substrate and their desired doping levels. For control purposes, in order to render these deviations less significant, the doping of P well 1 is at least an order of magnitude greater than the doping of N substrate 2, thereby insuring that, regardless of processing variations, P well 1 will have a sufficiently high concentration of P type dopants.
Problems of scale emerged from the prior art structure as the device density i.e., the number of devices per unit area, was increased. For example, as the distance between the P+ source and drain regions 8 and 9 of device 7 is reduced, the doping of N substrate 2 must increase to obtain appropriate electrical parameters, such as device threshold voltage, in the shorter channel length P channel transistor 7. However, increasing the doping of N substrate 2 requires a corresponding proportional increase in the doping level of P well 1 for control purposes as explained above.
The increase in the doping level of P well 1 causes increased junction capacitance between N+ source and drain regions 4 and 5 and P well 1. In fact, for a single-sided junction under zero bias, the junction capacitance varies directly as the square root of the dopant concentration on the lightly doped side of the junction, as shown in MOS INTEGRATED CIRCUITS, pgs. 45 and 46, Engineering Staff of American Micro-Systems, Robert E. Krieger Pub. Co., Malibu, Fla. (1979), which is incorporated herein by reference. In turn this increased capacitance has the undesirable effect of reducing the switching speed of transistor 3.
In order to overcome these problems of scale, a twin-tub CMOS technology was developed by Parrillo, et al., in "TWIN-TUB CMOS-A TECHNOLOGY FOR VLSI CIRCUITS", IEEE Tech Dig., Int. Electron Device Meet., 1980, p. 752-755 which is incorporated herein by reference. FIG. 1b illustrates the Parillo Twin-tub structure.
The Parillo structure includes lightly doped epitaxial region 20 formed on an N+ substrate 21. The use of an N+ substrate reduces the substrate resistance and prevents "latch-up", a term which refers to the turning on of "parasitic" bipolar transistors within the structure shown in FIG. 1b as will be explained later.
Both a P well 23 and an N well 24 are then formed in the epitaxial layer 20 by ion implantation. This is accomplished in a self-aligned manner by first defining an oxide-nitride mask (not shown), implanting and selectively oxiding N well 24, removing the remaining mask and implanting P well 23 self-aligned to the oxide masked N well 24.
The P well 23 and N well 24 are doped independently in order to optimize the performance characteristics of the active devices formed in P well 23 and N well 24, respectively. For example, the active devices may include transistor 28 having gate 27, gate dielectric layer 33 and source and drain regions 25 and 26, respectively, formed in P well 23 and transistor 32 having gate 31, gate dielectric layer 33, and source and drain regions 29 and 30 formed in N well 24. Thus it can be seen that increasing the doping of N well 24 to accommodate a decrease in the dimensional parameters of the P channel device 32 no longer necessitates a corresponding increase in the dopant concentration of P well 23. Of importance, parasitic bipolar transistors exist within this twin well structure. For example, an NPN parasitic transistor is formed by N+ region 26, P well 23, and N+ substrate 21. However, the N+ substrate has low resistivity and thus prevents "latch-up". Latch-up is a well-known problem, an analysis of which is presented in an article entitled "Elimination of Latch-up in Bulk CMOS", IEDM Paper 10.2, Dec. 8-10, Washington, D.C., which is incorporated herein by reference.
Both N well 24 and P well 23 in the prior art twin-tub structure described by Parillo are heavily doped. Parillo uses a dopant concentration of about 10.sup.16 atoms/cm.sup.3 at the surface of each well. Because of the relatively high doping in both wells, this structure is not well suited to integration with devices such as transistors, diodes, or resistors which are designed to operate at high voltages, say greater than 20 volts. In particular the prior art twin-tub structure is not suited for the integration of erasable programmable read only memories (EPROMS) or with electrically erasable programmable read only memories (EEPROMS) which require junction breakdown voltages greater than approximately 20 volts.
In addition to the need for providing both high and low voltage devices on the same chip, and thus providing a variety of doping levels for different wells, it is desirable to develop methods for forming structures which are faster and less expensive, and allow for forming smaller devices while retaining high yield. Various prior art methods have been developed to accomplish the objective of providing on the same chip different doping levels and dopants for different wells.
A method shown in FIGS. 2a and 2b forms multiple windows in a nitride/oxide layer, exposing the surface to permit the subsequent formation of diffusion isolation regions, base regions, and collector contact regions in the semiconductor body. The areas are masked, exposed, and doped in a predetermined sequence. The original areas of oxide/nitride, which were left between windows serve to define the edges of the wells, and on these areas of oxide/nitride the edges of successive photoresist masks are defined. Mask misalignment tolerances can be less stringent because the edges of the masks are formed over the previously formed areas of nitride/oxide and the nitride/oxide serves to define the edge of the well. U.S. Pat. No. 3,928,081 to Marley, Jr., et al., shows such a method for eliminating mask misalignment tolerances.
As shown in FIGS. 3a and 3b, U.S. Pat. No. 4,450,021, issued to Batra, et al., one of the coinventors of this application, uses a mask 109 for defining regions 110 to be doped and uses the same mask for depositing a protective layer 111 over the doped regions. With this arrangement, the alignment of the edge of the protective layer 111 is assured, because the edge of the oxide defines the area to be doped. When the mask is removed, the second regions 112 which are now exposed are automatically aligned to be doped without interfering with the first regions which are covered by protective layer 111. By this method it is possible to achieve doping of two wells with one masking step, thus saving the time of applying and defining the mask and thus also achieving automatic self-alignment of the areas to be doped. The method shown in this prior art patent is described as being applicable to implanting source and drain regions in the chip.
Thus, use of portions of the device as a mask for forming later portions is a well-known method of preventing misalignment.
Cerofolini, et al., in U.S. Pat. No. 4,277,291, discloses a different method, shown in FIGS. 4a and 4b, which could be used for forming adjacent, self-aligned N and P wells in which a heavily N-doped oxide mask is in place during P-doping and diffusion. The N-doped oxide mask prevents doping of the masked portion during the P-doping step and then produces diffusion of the N-dopant from the doped oxide into the substrate at the same time the P-doped region is being diffused into the substrate, resulting in simultaneous formation of self-aligned N and P wells.